Memory-mapped I/O (MMIO) and port-mapped I/O (PMIO) are two complementary strategies of performing enter/output (I/O) between the central processing unit (CPU) and peripheral devices in a computer (usually mediating entry via chipset). Another approach is utilizing dedicated I/O processors, Memory Wave Program generally generally known as channels on mainframe computer systems, which execute their very own directions. The memory and registers of the I/O gadgets are mapped to (associated with) deal with values, so a memory tackle may confer with both a portion of bodily RAM or to Memory Wave Program and registers of the I/O system. Every I/O device both displays the CPU's handle bus and responds to any CPU access of an handle assigned to that device, connecting the system bus to the specified gadget's hardware register, or uses a dedicated bus. To accommodate the I/O devices, some areas of the address bus used by the CPU should be reserved for I/O and must not be accessible for normal physical memory; the vary of addresses used for I/O gadgets is decided by the hardware.
The reservation could also be everlasting, or short-term (as achieved by way of financial institution switching). An example of the latter is found within the Commodore 64, which uses a form of memory mapping to trigger RAM or I/O hardware to seem within the 0xD000-0xDFFF range. Port-mapped I/O usually uses a particular class of CPU instructions designed particularly for performing I/O, such because the in and out instructions discovered on microprocessors primarily based on the x86 structure. Completely different varieties of those two instructions can copy one, two or four bytes (outb, outw and outl, respectively) between the EAX register or one in every of that register's subdivisions on the CPU and a specified I/O port deal with which is assigned to an I/O machine. I/O gadgets have a separate deal with space from general memory, either completed by an additional "I/O" pin on the CPU's physical interface, or a complete bus devoted to I/O. Because the tackle space for I/O is isolated from that for important memory, that is sometimes known as remoted I/O.
On the x86 architecture, index/data pair is often used for port-mapped I/O. Different CPU-to-device communication strategies, comparable to memory mapping, don't affect the direct memory entry (DMA) for a system, because, by definition, DMA is a memory-to-gadget communication method that bypasses the CPU. Hardware interrupts are one other communication methodology between the CPU and peripheral devices, however, for a lot of causes, interrupts are at all times handled individually. An interrupt is system-initiated, versus the strategies talked about above, that are CPU-initiated. It is usually unidirectional, as info flows solely from gadget to CPU. Lastly, each interrupt line carries only one bit of data with a hard and fast that means, particularly "an event that requires attention has occurred in a gadget on this interrupt line". I/O operations can gradual memory entry if the tackle and data buses are shared. It is because the peripheral machine is usually much slower than essential memory. In some architectures, port-mapped I/O operates by way of a dedicated I/O bus, alleviating the issue.
One benefit of memory-mapped I/O is that, by discarding the extra complexity that port I/O brings, a CPU requires less internal logic and is thus cheaper, quicker, simpler to build, consumes less power and may be bodily smaller; this follows the fundamental tenets of diminished instruction set computing, and can also be advantageous in embedded systems. The other benefit is that, as a result of regular memory instructions are used to handle units, all of the CPU's addressing modes can be found for the I/O as nicely because the memory, and directions that perform an ALU operation straight on a memory operand (loading an operand from a memory location, storing the result to a memory location, or Memory Wave each) can be used with I/O system registers as nicely. In distinction, port-mapped I/O directions are sometimes very limited, typically offering only for simple load-and-retailer operations between CPU registers and i/O ports, so that, for instance, so as to add a continuing to a port-mapped machine register would require three instructions: read the port to a CPU register, add the fixed to the CPU register, and write the result back to the port.